 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 32-bit tx system risc tx03 series tmpm380fydfg TMPM380FWDFG tmpm380fyfg tmpm380fwfg tmpm382fwfg tmpm382fsfg semiconductor company
revision history date revision 2011/3/17 rev 1 first release tmpm380/m382 tmpm380/m380 - 1 / 7 - *************************************************************************************************************** arm, arm powered, amba, ad k, arm9tdmi, tdmi, primecell, realview, thumb, cortex, coresight, arm9, arm926ej-s, embedded trace ma crocell, etm, ahb, apb, and keil are registered trademarks or trademarks of arm limited in the eu and other countries. **************************************************************************************************************** ? 1 over and features tmpm380/m382 tmpm380/m382 - 2 / 7 - comparison table ? tmpm382fwfg tmpm382fsfg tmpm380fyfg/dfg tmpm380fwfg/dfg (1) processor core arm cortex-m3 (2) interrupt sources - internal: 55 factors - external: 8 factors int0/1/2/3/4/5/8/f - internal: 77 factors - external: 16 factors int0-f (3) input/output ports 48 pins - input/output: 47 pins - output: 1pin 84 pins - input/output: 83 pins - output: 1pin (4) watchdog timer (wdt) 1 channel (5) power-on reset circuit (por) 1 channel (6) voltage detection circuit (vltd) 1 channel (7) oscillation frequency detector (ofd) 1 channel (8) dma contorller 2 channels (9) encoder input circuit (enc) 2 channels (10) 16-bit multi purpose timer (mpt) 1 channel ch0 3 channels ch0-2 (11) 16-bit timer (tmrb) 8 channels ch0-7 (ch3,5:16bit interval timer mode only) 8 channels ch0-7 (12) real time clock (rtc) 1 channel (13) serial channel (uart/sio) 3 channels ch0/1/4 5 channels ch0-4 (14) serial bus interface (i2c/sio) 1 channel ch0 2 channels ch0-1 (15) synchronous serial port (ssp) 1 channel ch0 2 channels ch0-1 (16) remote control signal preprocesser (rmc) 1 channel (17) 12-bit a/d converter (adc) 1unit - 10 channels ch0-9 1unit - 18 channels ch0-17 (18) standby mode - standby modes: idle, sleep and stop - sub clock operation (32.768khz): slow, sleep (19) clock generator(cg) 1 channel (20) endian little endian (21) maximum operating frequency 40mhz (22) operating voltage range 4.0v~5.5v (with on-chip regulator) (23) temperature range -40c~85c (except during flash writing/ erasing and debugging) 0c~70c (during flash writing/ erasing and degugging) tmpm380/m382 tmpm380/m382 - 3 / 7 - 32-bit risc microcontroller tx03 series tmpm380fyfg, tmpm380fwfg tmpm380fydfg, TMPM380FWDFG tmpm382fwfg, tmpm382fsfg tx03 series is a 32-bit risc microcontroller series with an arm ? cortex?-m3 microcontroller core. product no. on chip flash rom on chip ram package tmpm380fyfg 256 kbyte 16 kbyte lqfp100-p-1414-0.50h tmpm380fydfg 256 kbyte 16 kbyte qfp100-p-1420-0.65q tmpm380fwfg 128 kbyte 12 kbyte lqfp100-p-1414-0.50h TMPM380FWDFG 128 kbyte 12 kbyte qfp100-p-1420-0.65q tmpm382fwfg 128 kbyte 12 kbyte qfp64-p-1414-0.80c tmpm382fsfg 64 kbyte 8 kbyte qfp64-p-1414-0.80c 1.1 features (1) arm cortex-m3 microcontroller core 1) improved cod e efficiency has been realized through the use of thumb ? -2 instruction - new 16-bit thumb ? instructions for improved program flow - new 32-bit thumb instructions for improved performance - auto-switching between 32-bit instruction and 16-bit instruction is executed by compiler. 2) both high performance and low power consumption have been achieved ? high performance - a 32-bit multiplication (3232=32 bi t) can be executed with one clock - division takes between 2 and 12 cycles depending on dividend and devisor ? low power consumption - optimized design using a low power consumption library - standby function that stops the operat ion of the microcontroller core 3) high-speed interrupt response suitable for real-time control - an interruptible long instruction - stack push automatically handled by hardware (2) interrupt sources - internal: 77 fa ctors?t he order of precedenc e can be set over 7 levels (except nmi). - external: 16 factors?the order of precedence can be set over 7 levels (3) input/output ports 84 pins - input/output: 83 pin s output: 1pin (4) watchdog timer (wdt): 1 channel - bina ry cou nter :under development 1 over and features tmpm380/m382 tmpm380/m382 - 4 / 7 - (5) power-on reset circuit (por) (6) v o ltage detection circuit (vltd) (7) oscillation f r equency detector (ofd) (8) dma contorll er: 2 channels - inc r to incr / incr to no-incr / no-incr to incr / no-incr to no-incr - 4word fifo buffer for each channel *2ch - scatter/gather transmission support (9) encoder input circuit (enc): 2 channels - co rre spond to increamental encoder(ab/abz) - rotation direction detecttion - counter for absolute position detection - comparator for position detection - noise filter - 3 phase sensor input (10) 16-bit multi purpose timer (mpt) : 3 channels cha nnel 0/1: suppo rted for pmd fucntion / igbt function / 16bit timer function channle 2: supported for igbt function / 16bit timer function pmd function - 3-phase pwm waveforms with the same pwm frequency - synctrigger signals to the ad converter - the protection circuit controls in emergency igbt function - 16-bit ppg output (two output pins) - external-triggered start and stop - the protection circuit controls in emergency 16bit timer function - 16-bit interval timer mode - 16-bit event counter mode - 16-bit ppg output (one output pin) - input capture function (11) 16-bit timer (tmrb): 8 channels - 16-bit interval timer mode - 16-bit event counter mode - 16-bit ppg output - external trigger programmable square-wave output mode (ppg) - timer synchronous mode - input capture function (12) real time clock (rtc) - clo ck (hour, minute and second) - calender (month, week, date and leap year) - alarm (alarm output) - alarm interruption (13) serial channel (uart/sio): 5 channels - either ua rt mode o r synchronous mode can be selected (4byte fifo equipped) tmpm380/m382 tmpm380/m382 - 5 / 7 - (14) serial bus interface (i2c/sio): 2 channels - either i2c bus mod e or synchronous mode can be selected (15) synchronous serial port (ssp): 2 channels - spi flame format /ssi flame format /mic rowire flame format - 16byte fifo equipped (16bit*8) (16) remote control signal preprocesser (rmc) : 1 channel - can re ceive up to 72bit data at a time (17) 12-bit a/d converter (adc): 1unit (18 channels for analog input) - start by the intern al trigge r: tmrb interrupt / pmd trigger - 3 conversion mode(trigger start,so ftware start,constant conversion) arbitrary ain can be selected - ad conversion result register (12ch) - ad conversion monitoring function (2ch) - conversion speed 2.0usec (@ adc conversion clock = 40mhz) (18) standby mode - s t andby modes: idle, sleep and stop - sub clock operation (32.768khz): slow, sleep (19) clock generator(cg) - external osci illator (high f req. 10mhz x?ta l/ceramic) or on-chi p oscillator (9mhz) - external oscillator (low freq. 32khz x?tal) - on-chip pll (4 times) - clock gear function: the high-speed clock can be divided into 1/1, 1/2, 1/4, 1/8, 1/16 (20) endian - little endian (21 ) maximum operating frequency - 40m hz (22 ) operating voltage range - 4.0v~5.5v (with on-chip re gulato r) (23) temperature range - -40 c~85c (except during flash writing/ erasing and debugging) - 0c~70c (during flash writing/ erasing and degugging) 1 over and features tmpm380/m382 tmpm380/m382 - 6 / 7 - 1.2 block diagram fig1-1 tmpm380 block diagram cortex-m3 cpu debug nvic bus bridge i-code d-code system ahb-bus-matrix (40mhz) io-bus mpt(3ch) tmrb(8ch) ssp(2ch) uart/sio(5ch) por ofd wdt rtc cg enc (2ch) adc(18ch) rmc (1ch) regulator 3.3v nano flash i/f ram i/f i/f boot rom 5v 1.5v high-speed oscillator pll i2c/sio(2ch) dmac(2ch) int. high-speed oscillator port a - p vltd low-speed oscillator tmpm380/m382 tmpm380/m382 - 7 / 7 - fig1-1 tmpm382 block diagram cortex-m3 cpu debug nvic bus bridge i-code d-code system ahb-bus-matrix (40mhz) io-bus mpt(1ch) tmrb(8ch) ssp(1ch) uart/sio(3ch) por ofd wdt rtc cg adc(10ch) rmc (1ch) regulator 3.3v nano flash i/f ram i/f i/f boot rom 5v 1.5v high-speed oscillator pll i2c/sio(1ch) dmac(2ch) int. high-speed oscillator port a - p vltd low-speed oscillator tmpm380/m382 tmpm380/m382 - 1 / 13 - 2 pin layout and pin functions this chapter describes the pin layout, pin names and pin functions of tmpm380fyfg, tmpm380fwfg, tmpm380fydfg,TMPM380FWDFG tmpm382fwfg and tmpm382fsfg. 2.1 pin layout (top view) fig.2-1 shows the pin layout of tmpm380fyfg and tmpm380fwfg. fig. 2-1 pin layout (tmpm380fxfg) tmpm380fyfg tmpm380fwfg 100pin (14x14) top view pd5/txd2 pd6/rxd2 pf4/encz1/rxd3 pf3/encb1/txd3 pf2/enca1/sclk3/cts3 pf1/tb7out/alarm pf0/tb7in pb7/trst pb6/tdi pb5/tdo/swv pb4/tck/swclk pb3/tms/swdio pb2/tracedata1 pb1/tracedata0 pb0/traceclk ftest3 pl0/boot dvdd5 dvss a vdd5 a vss pj7/ain17/intb pj6/ain16/inta pj5/ain15 pj4/ain14 pd4/sclk2/cts2 pd3/int9 pd2/encz0/intd pd1/encb0/tb5out pd0/enca0/tb5in/intc dvss pc7/mt0in/rxd4 pc6/emg0/gemg0 / txd4 pc5/z o 0/mtout10/mttb0in/sclk4/cts4 pc4/wo0/mtout00/mttb0out pc3/yo0/sp0fss pc2/vo0/sp0clk/sck0 pc1/xo0/sp0di/scl0/si0 pc0/uo0/sp0do/sda0/so0 dvdd5 pp1/xt2 pp0/xt1 pm1/x2 dvss pm0/x1 dvss pg0/uo1/sda1/so1 pg1/xo1/scl1/si1 pg2/vo1/sck1 pg3/yo1 pj3/ain13 pj2/ain12 pj1/ain11 pj0/ain10 pi1/ain9 pi0/ain8 ph7/ain7 ph6/ain6 ph5/ain5 ph4/ain4 ph3/ain3 ph2/ain2/int2 ph1/ain1/int1 ph0/ain0/int0 vout3 reset rvdd5 mode dvss pl2/intf pn7/mt2in/inte pn6/gemg2 pn5/mtout12/mttb2in pn4/mtout02/mttb2out pn3/sp1fss pg4/wo1/mtout01/mttb1out pg5/zo1/mtout11/mttb1in pg6/emg1/gemg1 pg7/mt1in pa0/tb0in/int3 pa1/tb0out/scout pa2/tb1in/int4 pa3/tb1out/rxin pa4/sclk1/cts1 pa5 /txd1/tb6out pa6/rxd1/tb6in pa7/tb4in/int8 pe0/txd0 pe1/rxd0 pe2/sclk0/cts0 pe3/tb4out dvdd5 pe4/tb2in/int5 pe5/tb2out dvss pe6/tb3in/int6 pe7/tb3out/int7 pn0/sp1do pn1/sp1di pn2/sp1clk 1 5 10 15 20 25 75 70 65 60 55 51 26 30 35 40 45 50 100 95 90 85 80 76 2 pin layout and pin functions tmpm380/m382 tmpm380/m382 - 2 / 13 - fig.2-2 shows the pin layout of tmpm380fydfg and TMPM380FWDFG. fig. 2-2 pin layout (tmpm380fxdfg) 1 5 10 15 20 25 30 80 75 70 65 60 55 51 31 35 40 45 50 100 95 90 85 81 tmpm380fydfg TMPM380FWDFG 100pin (14x20) top view pf4/encz1/rxd3 pf3/encb1/txd3 pf2/enca1/sclk3/cts3 pf1/tb7out/alarm pf0/tb7in pb7/trst pb6/tdi pb5/tdo/swv pb4/tck / swclk pb3/tms/swdio pb2/tracedata1 pb1/tracedata0 pb0/traceclk ftest3 pl0/boot dvdd5 dvss a vdd5 a vss pj7/ain17/intb pd6/rxd2 pd5/txd2 pd4/sclk2/cts2 pd3/int9 pd2/encz0/intd pd1/encb0/tb5out pd0/enca0/tb5in/intc dvss pc7/mt0in/rxd4 pc6/emg0/gemg0 / txd4 pc5/zo0/mtout10/mttb0in/sclk4/cts4 pc4/wo0/mtout00/mttb0out pc3/yo0/sp0fss pc2/vo0/sp0clk/sck0 pc1/xo0/sp0di/scl0/si0 pc0/uo0/sp0do/sda0/so0 dvdd5 pp1/xt2 pp0/xt1 pm1/x2 dvss pm0/x1 dvss pg0/uo1/sda1/so1 pg1/xo1/scl1/si1 pg2/v1/sck1 pg3/yo1 pg4/wo1/mtout01/mttb1out pg5/zo1/mtout11/mttb1in pg6/emg1/gemg1 pj6/ain16/inta pj5/ain15 pj4/ain14 pj3/ain13 pj2/ain12 pj1/ain11 pj0/ain10 pi1/ain9 pi0/ain8 ph7/ain7 ph6/ain6 ph5/ain5 ph4/ain4 ph3/ain3 ph2/ain2/int2 ph1/ain1/int1 ph0/ain0/int0 vout3 reset rvdd5 mode dvss pl2/intf pn7/mt2in/inte pn6/gemg2 pn5/mtout12/mttb2in pn4/mtout02/mttb2out pn3/sp1fss pn2/sp1clk pn1/sp1di pg7/mt1in pa0/tb0in/int3 pa1/tb0out/scout pa2/tb1in/int4 pa3/tb1out/rxin pa4/sclk1/cts1 pa5 /txd1/tb6out pa6/rxd1/tb6in pa7/tb4in/int8 pe0/txd0 pe1/rxd0 pe2/sclk0/cts0 pe3/tb4out dvdd5 pe4/tb2in/int5 pe5/tb2out dvss pe6/tb3in/int6 pe7/tb3out/int7 pn0/sp1do tmpm380/m382 tmpm380/m382 - 3 / 13 - fig.2-3 shows the pin layout of tmpm382fwfg and tmpm382fsfg. fig. 2-3 pin layout (tmpm382fxfg) tmpm382fwfg tmpm382fsfg 64pin (14x14) top view pf1/tb7out/alarm pf0/tb7in pb7/trst pb6/tdi pb5/tdo/swv pb4/tck/swclk pb3/tms/swdio pb2/tracedata1 pb1/tracedata0 pb0/traceclk ftest3 pl0/boot dvdd5 dvss a vdd5 a vss dvss pc7/mtin/rxd4 pc6/emg0/gemg0 / txd4 pc5/zo0/mtout10/mttb0in/sclk4/cts4 pc4/wo0/mtout00/mttb0out pc3/yo0/sp0fss pc2/vo0/sp0clk/sck0 pc1/xo0/sp0di/scl0/si0 pc0/uo0/sp0do/sda0/so0 dvdd5 pp1/xt2 pp0/xt1 pm1/x2 dvss pm0/x1 dvss pi1/ain9 pi0/ain8 ph7/ain7 ph6/ain6 ph5/ain5 ph4/ain4 ph3/ain3 ph2/ain2/int2 ph1/ain1/int1 ph0/ain0/int0 vout3 reset rvdd5 mode dvss pl2/intf pa0/tb0in/int3 pa1/tb0out/scout pa2/tb1in/int4 pa3/tb1out/rxin pa4/sclk1/cts1 pa5 /txd1/tb6out pa6/rxd1/tb6in pa7/tb4in/int8 pe0/txd0 pe1/rxd0 pe2/sclk0/cts0 pe3/tb4out dvdd5 pe4/tb2in/int5 pe5/tb2out dvss 1 5 10 15 48 45 40 35 17 20 25 30 32 64 60 55 50 2 pin layout and pin functions tmpm380/m382 tmpm380/m382 - 4 / 13 - 2.2 pin function table 2-1 lists the pin functions of tmpm380fxfg/dfg. table 2-4 shows the operating voltage of each pin, and table 2-5 show s the volt age range of every pin. table 2-1 pin functions (1/5) m380fxdfg qfp100 m380fxfg lqfp100 pin name output during reset schimitt (o:yes) open drain mode 3 1 pd4 sclk2 cts2 hi-z o o 4 2 pd3 int9 hi-z o o 5 3 pd2 encz0 intd hi-z o o 6 4 pd1 encb0 tb5out hi-z o o 7 5 pd0 enca0 tb5in intc hi-z o o 8 6 dvss 9 7 pc7 mt0in rxd4 hi-z o o 10 8 pc6 emg0 gemg0 txd4 hi-z o o 11 9 pc5 zo0 mtout10 mttb0in sclk4 cts4 hi-z o o 12 10 pc4 wo0 mtout00 mttb0out hi-z o o 13 11 pc3 yo0 sp0fss hi-z o o 14 12 pc2 vo0 sp0clk sck0 hi-z o o 15 13 pc1 xo0 sp0di scl0 / si0 hi-z o o tmpm380/m382 tmpm380/m382 - 5 / 13 - table 2-1 pin functions (2 /5) m380fxdfg qfp100 m380fxfg lqfp100 pin name output during reset schimitt (o:yes) open drain mode 16 14 pc0 uo0 sp0do sda0 / so0 hi-z o o 17 15 dvdd5 18 16 pp1 xt2 hi-z o o 19 17 pp0 xt1 hi-z o o 20 18 pm1 x2 hi-z o o 21 19 dvss 22 20 pm0 x1 hi-z o o 23 21 dvss 24 22 pg0 uo1 sda1 / so1 hi-z o o 25 23 pg1 xo1 scl1 / si1 hi-z o o 26 24 pg2 vo1 sck1 hi-z o o 27 25 pg3 yo1 hi-z o o 28 26 pg4 wo1 mtout01 mttb1out hi-z o o 29 27 pg5 zo1 mtout11 mttb1in hi-z o o 30 28 pg6 emg1 gemg1 hi-z o o 31 29 pg7 mt1in hi-z o o 32 30 pa0 tb0in int3 hi-z o o 33 31 pa1 tb0out scout hi-z o o 34 32 pa2 tb1in int4 hi-z o o 35 33 pa3 tb1out rxin hi-z o o 2 pin layout and pin functions tmpm380/m382 tmpm380/m382 - 6 / 13 - table 2-1 pin functions (3 /5) m380fxdfg qfp100 m380fxfg lqfp100 pin name output during reset schimitt (o:yes) open drain mode 36 34 pa4 sclk1 cts1 hi-z o o 37 35 pa5 txd1 tb6out hi-z o o 38 36 pa6 rxd1 tb6in hi-z o o 39 37 pa7 int8 tb4in hi-z o o 40 38 pe0 txd0 hi-z o o 41 39 pe1 rxd0 hi-z o o 42 40 pe2 sclk0 cts0 hi-z o o 43 41 pe3 tb4out hi-z o o 44 42 dvdd5 45 43 pe4 tb2in int5 hi-z o o 46 44 pe5 tb2out hi-z o o 46 45 dvss 48 46 pe6 tb3in int6 hi-z o o 49 46 pe7 tb3out int7 hi-z o o 50 48 pn0 sp1do hi-z o o 51 49 pn1 sp1di hi-z o o 52 50 pn2 sp1clk hi-z o o 53 51 pn3 sp1fss hi-z o o 54 52 pn4 mtout02 mttb2out hi-z o o 55 53 pn5 mtout12 mttb2in hi-z o o 56 54 pn6 gemg2 hi-z o o tmpm380/m382 tmpm380/m382 - 7 / 13 - table 2-1 pin functions (4 /5) m380fxdfg qfp100 m380fxfg lqfp100 pin name output during reset schimitt (o:yes) open drain mode 57 55 pn7 mt2in inte hi-z o o 58 56 pl2 intf hi-z o o 59 57 dvss 60 58 mode hi-z o 61 59 rvdd5 62 60 reset pull up o 63 61 vout3 vout3 64 62 ph0 ain0 int0 hi-z o o 65 63 ph1 ain1 int1 hi-z o o 66 64 ph2 ain2 int2 hi-z o o 67 65 ph3 ain3 hi-z o o 68 66 ph4 ain4 hi-z o o 69 67 ph5 ain5 hi-z o o 70 68 ph6 ain6 hi-z o o 71 69 ph7 ain7 hi-z o o 72 70 pi0 ain8 hi-z o o 73 71 pi1 ain9 hi-z o o 74 72 pj0 ain10 hi-z o o 75 73 pj1 ain11 hi-z o o 76 74 pj2 ain12 hi-z o o 77 75 pj3 ain13 hi-z o o 78 76 pj4 ain14 hi-z o o 79 77 pj5 ain15 hi-z o o 80 78 pj6 ain16 inta hi-z o o 81 79 pj7 ain17 intb hi-z o o 2 pin layout and pin functions tmpm380/m382 tmpm380/m382 - 8 / 13 - table 2-1 pin function (5/ 5 ) m380fxdfg qfp100 m380fxfg lqfp100 pin name output during reset schimitt (o:yes) open drain mode 82 80 avss 83 81 avdd5 84 82 dvss 85 83 dvdd5 86 84 pl0 boot pull up o 87 85 ftest3 hi-z(note) 88 86 pb0 traceclk hi-z o o 90 87 pb1 tracedata0 hi-z o o 90 88 pb2 tracedata1 hi-z o o 91 90 pb3 tms swdio pull up o o 92 90 pb4 tck swclk pull down o o 93 91 pb5 tdo swv hi-z o o 94 92 pb6 tdi pull up o o 95 93 pb7 trst pull up o o 96 94 pf0 tb7in hi-z o o 97 95 pf1 tb7out alarm hi-z o o 98 96 pf2 enca1 sclk3 cts3 hi-z o o 99 97 pf3 encb1 txd3 hi-z o o 100 98 pf4 encz1 rxd3 hi-z o o 1 99 pd6 rxd2 hi-z o o 2 100 pd5 txd2 hi-z o o (note) open : don?t connect any circuit. this pin use for internal test only. tmpm380/m382 tmpm380/m382 - 9 / 13 - table 2-2 lists the pin functions of tmpm382fxfg. table 2-4 show s the operating voltage of each pin, and table 2-5 show s the voltage range of every pin. table 2-2 pin functions (1/4) pin no. pin name output during reset schimitt (o:yes) open drain mode 1 dvss 2 pc7 mtin rxd4 hi-z o o 3 pc6 emg0 gemg0 txd4 hi-z o o 4 pc5 zo0 mtout10 mttb0in sclk4 cts4 hi-z o o 5 pc4 wo0 mtout00 mttb0out hi-z o o 6 pc3 yo0 sp0fss hi-z o o 7 pc2 vo0 sp0clk sck0 hi-z o o 8 pc1 xo0 sp0di scl0 / si0 hi-z o o 9 pc0 uo0 sp0do sda0 / so0 hi-z o o 10 dvdd5 11 pp1 xt2 hi-z o o 12 pp0 xt1 hi-z o o 13 pm1 x2 hi-z o o 14 dvss 15 pm0 x1 hi-z o o 16 dvss 2 pin layout and pin functions tmpm380/m382 tmpm380/m382 - 10 / 13 - table 2-3 pin functions (2/4) pin no. pin name output during reset schimitt (o:yes) open drain mode 17 pa0 tb0in int3 hi-z o o 18 pa1 tb0out scout hi-z o o 19 pa2 tb1in int4 hi-z o o 20 pa3 tb1out rxin hi-z o o 21 pa4 sclk1 cts1 hi-z o o 22 pa5 txd1 tb6out hi-z o o 23 pa6 rxd1 tb6in hi-z o o 24 pa7 int8 tb4in hi-z o o 25 pe0 txd0 hi-z o o 26 pe1 rxd0 hi-z o o 27 pe2 sclk0 cts0 hi-z o o 28 pe3 tb4out hi-z o o 29 dvdd5 30 pe4 tb2in int5 hi-z o o 31 pe5 tb2out hi-z o o 32 dvss tmpm380/m382 tmpm380/m382 - 11 / 13 - table 2-2 pin function s (3/ 4) pin no. pin name output during reset schimitt (o:yes) open drain mode 33 pl2 intf hi-z o o 34 dvss 35 mode hi-z o 36 rvdd5 37 reset pull up o 38 vout3 vout3 39 ph0 ain0 int0 hi-z o o 40 ph1 ain1 int1 hi-z o o 41 ph2 ain2 int2 hi-z o o 42 ph3 ain3 hi-z o o 43 ph4 ain4 hi-z o o 44 ph5 ain5 hi-z o o 45 ph6 ain6 hi-z o o 46 ph7 ain7 hi-z o o 47 pi0 ain8 hi-z o o 48 pi1 ain9 hi-z o o 2 pin layout and pin functions tmpm380/m382 tmpm380/m382 - 12 / 13 - table 2-2 pin function (4/4) pin no. pin name output during reset schimitt (o:yes) open drain mode 49 avss 50 avdd5 51 dvss 52 dvdd5 53 pl0 boot pull up o 54 ftest3 hi-z(note) 55 pb0 traceclk hi-z o o 56 pb1 tracedata0 hi-z o o 57 pb2 tracedata1 hi-z o o 58 pb3 tms swdio pull up o o 59 pb4 tck swclk pull down o o 60 pb5 tdo swv hi-z o o 61 pb6 tdi pull up o o 62 pb7 trst pull up o o 63 pf0 tb7in hi-z o o 64 pf1 tb7out alarm hi-z o o (note) open : don?t connect any circuit. this pin use for internal test only. tmpm380/m382 tmpm380/m382 - 13 / 13 - table 2-4 operating voltage of each pin pin name operating voltage function pm0,pm1 x1,x2 dvdd5 internal 1.5v x1 can?t be driven by outside oscillator. pp0,pp1 xt1,xt2 dvdd5 internal 1.5v xt1 can?t be driven by outside oscillator. reset mode must be connected to gnd pa to pg,pl,pn i/o dvdd5 ph,pi,pj ain0 to ain17 avdd5(vrefh) table 2-5 voltage range of each pin pin name voltage range function rvdd5 for internal circuit dvdd5 for i/o ports avdd5 4.0 5.5v for adc vout3 2.7 3.6v output terminal of internal power supply. connected to dvss through 1 to 4.7f capacito r dvss avss gnd note : vout3 can't supply the power supply to an external circuit. tmpm380/m382 tmpm380/m382 - 1 / 2- 3 processor core 3.1 processor core the tx03 series has a high-performance 32-bit processor core (the arm cortex-m3 processor core). for information on the operations of this processor core, please refer to the ?cortex-m3 technical reference manual? issued by arm limited. this chapter describes the functions unique to the tx03 series that are no t explained in that document. the following table shows the revision of the proc essor core in the tmpm380/m382. for further information on each revision, see the documents issued by arm limited. product name core revision tmpm380 r2p0-00rel0 tmpm382 r2p0-00rel0 3.2 configurable opions the cortex-m3 core has the optional blocks. the optional blocks of the revision r2p0 are below; optional block implementation fpb o dwt o itm o mpu x etm tm o ahb-ap o ahb trace macro-cell interface o tpiu o wic x o: implement x: not implement 3.3 event tmpm380/m382 does not support event input/output. do not use sev instruction and wfe instruction. 3.4 sleepdeepl tmpm380/m382 does not support sleepdeep. 3 processor core tmpm380/m382 tmpm380/m382 - 2 / 2 - 3.5 exclusive access tmpm380/m382 does not supp ort exclusive access. 3.6 reset operation 3.6.1 initial state the internal circuits, register settings and pin status are undefined right after the power-on. the state continues until the reset pin receives low level input after all the power supply voltage is applied. 3.6.2 reset operation as the precondition, ensure that an internal high-frequenc y oscillator provides stable oscillation while power supply voltage is in the operating range. to reset the tmpm380/m382, input reset signal at low level for a minimu m duration of 12 system clocks (1.2 s with external 10mhz oscillator). 3.6.3 after reset when the reset is released, the system control register and the internal i/o register of the cortex-m3 processor core are initialized. note that the pll multiplication circuit stops after releasing the reset. therefore, set cgosccr tmpm380/m382 tmpm380/m382 - 1 / 3 - 4 dubug interface 4.1 specification overview the tmpm380/m382 contains the serial wire jtag debug port (swj-dp) unit for interfacing with the in-circuit emulator (ice ) and the embedded trace macrocell tm (etm) unit for instruction trace output. trace data is output to the dedicated pins (tracedata[0]-[1], swv) via the on-chip trace port interface unit (tpiu). for details about swj-dp, etm and tpiu, refer to ?cortex-m3 technical reference manual?. 4.2 features of swj-dp swj-dp supports the two-pin serial wire de bug port (swdck, swdio) and the jtag debug port (tdi, tdo, tms, tck, trst). 4.3 features of etm etm supports two data signal pins (tracedata[0]-[1]), one clock signal pin (traceclk) and trace output from swv. 4.4 pin functions the debug interface pins can also be used as gen eral-purpose ports. the pb3 and pb4 are shared between the jtag debug port function and the serial wire debug port function. the pb5 is shared between the jtag debug port function and the swv trace output function. ? ()3, ? ? ? ? ? swj-dp etm ? function ? jtag debug function sw debug swj-dp pin name name of port i/o discription i/o discription tms/swdio pb3 input jtag test mode selection i/o serial wire data input/output tck/swclk pb4 input jtag test check input serial wire clock tdo/swv pb5 output jtag test data output (output) (note) (serial wire viewer output) tdi pb6 input jtag test data input trst --------------- pb7 input jtag test reset ------------------- traceclk pb0 output trace clock output tracedata0 pb1 output trace data output0 tracedata1 pb2 output trace data output1 (note) in case of enabling swv function. ? ? after reset, the pb3, pb4, pb5, pb6 and pb7 are configured as debug port function pins. the functions of other debug interface pins need to be programmed as required. debug interface pins can use general purpose port that is not use debug interface. 4 dubug interface tmpm380/m382 tmpm380/m382 - 2 / 3 - the table 4-2 below summarizes the debug interface pin functions and related port settings after reset. table 4-2 ? debug interface pins and port setting after reset port setting after reset initial setting port (bit name) debug function function (pbfr) input (pbie) output (pbcr) pull-up (pbpup) pull-down (pbpdn) port pb0 traceclk 0 0 0 0 0 port pb1 tarcedata0 0 0 0 0 0 port pb2 tracedata1 0 0 0 0 0 debug pb3 tms/swdio 1 1 1 1 0 debug pb4 tck/swclk 1 1 0 0 1 debug pb5 tdo/swv 1 0 1 0 0 debug pb6 tdi 1 1 0 1 0 debug pb7 trst --------------- 1 1 0 1 0 when using a low power consumption mode, take note of the following points. (note 1) if pb3 and pb5 are configured as debug function pins, output continues to be enabled even in stop mode regardless of t he setting of the cgstbycr tmpm380/m382 tmpm380/m382 - 3 / 3 - 4.6 peripherals operation during halt mode ( one time stop of running program) when cortex-m3 cpu core going into halt mode by break operation during debbug mode,watch dog timer(wdt) count stops automatically. other peripherals c ontinue operation. (note) 16-bit timer (tmrb) and multi purpose ti mer (mpts) can be desable in halt mode. please refer to ?16-bit timer (tmrb)? and ?16-bit multi-purpose timers (mpts)? tmpm380/m382 tmpm380/m382 - 1 / 4 - 5 memory map the memory maps for the tmpm380 are based on the arm cortex-m3 processor core memory map. the internal rom, internal ram and inter nal i/o of the tmpm380 are mapped to the code, sram and peripheral regions of the cortex-m3 resp ectively. the sram and internal i/o regions are all included in the bit-band region. the cpu register region is the processor core?s internal register region. for more information on each region, see the ?cortex-m3 technical reference manual?. note that access to regions indicated as ?fault? causes a memory fault if memory faults are enabled or a hard fault if memory faults are disabl ed. do not access the vendor-specific region. see ?special function registers? for details on the internal i/o region. 5 memory map tmpm380/m382 tmpm380/m382 - 2 / 4 - 5.1 tmpm380fy memory map fig 5-1 shows the memory map of the tmpm380fy. fig 5-1 mem o ry map single chip mode fault 0xffff ffff 0xe010 0000 0x41ff ffff 0x4000 0000 0xe00f ffff 0xe000 0000 internal io 0x0003 ffff 0x0000 0000 0x2000 3fff 0x2000 0000 vendor specific cpu register region fault internal ram (16k) fault ? internalrom (256k) ? internalrom (256k) internal io fault internalram (16k) fault bootrom (4k) ? 0x2000 3fff 0x2000 0000 0x41ff ffff 0x4000 0000 0x3f83 ffff 0x3f80 0000 0x0000 0fff 0x0000 0000 fault fault 0xffff ffff 0xe010 0000 0xe00f ffff 0xe000 0000 vendor specific cpu register region single boot mode tmpm380/m382 tmpm380/m382 - 3 / 4 - 5.2 tmpm380fw/382fw memory map fig 5-2 shows the memory map of the tmpm380fw/382fw. fig 5-2 mem o ry map single chip mode fault 0xffff ffff 0xe010 0000 0x41ff ffff 0x4000 0000 0xe00f ffff 0xe000 0000 internal io 0x0001 ffff 0x0000 0000 0x2000 2fff 0x2000 0000 vendor specific cpu register region fault internal ram (12k) fault ? internalrom (128k) ? internalrom (128k) internal io fault internalram (12k) fault bootrom (4k) ? 0x2000 2fff 0x2000 0000 0x41ff ffff 0x4000 0000 0x3f81 ffff 0x3f80 0000 0x0000 0fff 0x0000 0000 fault fault 0xffff ffff 0xe010 0000 0xe00f ffff 0xe000 0000 vendor specific cpu register region single boot mode 5 memory map tmpm380/m382 tmpm380/m382 - 4 / 4 - 5.3 tmpm382fs memory map fig 5-3 shows the memory map of the tmpm382fs. fig 5-3 mem o ry map single chip mode fault 0xffff ffff 0xe010 0000 0x41ff ffff 0x4000 0000 0xe00f ffff 0xe000 0000 internal io 0x0000 ffff 0x0000 0000 0x2000 1fff 0x2000 0000 vendor specific cpu register region fault internal ram (8k) fault ? internalrom (64k) ? internalrom (64k) internal io fault internalram (8k) fault bootrom (4k) ? 0x2000 1fff 0x2000 0000 0x41ff ffff 0x4000 0000 0x3f80 ffff 0x3f80 0000 0x0000 0fff 0x0000 0000 fault fault 0xffff ffff 0xe010 0000 0xe00f ffff 0xe000 0000 vendor specific cpu register region single boot mode tmpm380/m382 tmpm380/m382 - 1 / 24 6 clock/mode control 6.1 features the clock/mode control block enables to select clock gear, prescaler clock and warm-up of the pll (including clock multiplication circuit) and oscillator. the low power consumption mode can reduce power consumption.by mode transitions. this chapter describes how to control clocks, clock operating modes and mode transitions. the clock/mode control block ha s the following functions: y controls the oscillator y controls the system clock. y controls the prescaler clock. y controls the pll multiplication circuit. y controls the warm-up timer. in addition to normal mode, the tmpm380/m382 can operate in three types of low power mode to reduce power consumption according to its usage conditions. 6 clock/mode control tmpm380/m382 tmpm380/m382 - 2 / 24 - 6.2 registers 6.2.1 register list table 6-1 shows registers and addresses of the clock generator. table 6-1 registers of clock generator register name address system control regist er cgsyscr 0x4004_0200 oscillation control register cgosccr 0x4004_0204 standby control register cgstbycr 0x4004_0208 pll selection register cgpllsel 0x4004_020c system clock selection re gister cgcksel 0x4004_0210 tmpm380/m382 tmpm380/m382 - 3 / 24 6.2.2 detailed description of registers 6.2.2.1 system control register (cgsyscr: 0x4004_0200 ) 7 6 5 4 3 2 1 0 bit symbol - - - - - gear2 gear1 gear0 read/write r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 high-speed clock (fc) gear function ?0? is read. 000: fc 001: reserved 010: reserved 011: reserved 100: fc/2 101: fc/4 110: fc/8 111: fc/16 15 14 13 12 11 10 9 8 bit symbol - - fpsel1 fpsel0 - prck2 prck1 prck0 read/write r r/w r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 prescaler clock function ?0? is read. fperiph clock 00:fgear 01:fc 1*: fs ?0? is read. 000: fperiph 001: fperiph/2 010: fperiph/4 011: fperiph/8 100: fperiph/16 101: fperiph/32 110: reserved 111: reserved 23 22 21 20 19 18 17 16 bit symbol - - - fcstop - - scosel1 scosel0 read/write r/w r r/w r r/w r/w after reset 0 0 0 0 0 0 0 1 function wtite ?0? ?0? is read. fclk for adc 0:enable 1:disable ?0? is read. scout clock 00:fs 01:fsys/2 10:fsys 11: t0 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - read/write r after reset 0 0 0 0 0 0 0 0 function ?0? is read. 6 clock/mode control tmpm380/m382 tmpm380/m382 - 4 / 24 - 6.2.2.2 oscillation control register (cgosccr: 0x4004_0204) tmpm380/m382 tmpm380/m382 - 5 / 24 6 clock/mode control tmpm380/m382 tmpm380/m382 - 6 / 24 - 6.2.2.3 standby control register (cgstbycr: 0x4004_02 08) 7 6 5 4 3 2 1 0 bit symbol - - - - - stby2 stby1 stby0 read/write r r/w r/w r/w after reset 0 0 0 0 0 0 1 1 function ?0? is read. low power consumption mode 000: reserved 001: stop 010: sleep (note) 011: idle 1**: reserved 15 14 13 12 11 10 9 8 bit symbol - - - - - - rxten rxen read/write r r/w r/w after reset 0 0 0 0 0 0 0 1 function ?0? is read. low-speed oscillator after releasing stop mode 0: stop 1: oscillation high-speed oscillator after releasing stop mode 0: stop 1: oscillation 23 22 21 20 19 18 17 16 bit symbol - - - - - - - drve read/write r r/w r/w after reset 0 0 0 0 0 0 0 0 function ?0? is read. write ?000?. port drive in stop mode 0: hi-z 1: drive 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - read/write r after reset 0 0 0 0 0 0 0 0 function ?0? is read. tmpm380/m382 tmpm380/m382 - 7 / 24 6.2.2.4 pll selection register (cgpllsel: 0x4004_020c) 6 clock/mode control tmpm380/m382 tmpm380/m382 - 8 / 24 - 6.2.2.5 system clock selection register (cgcksel: 0x4004_0210) tmpm380/m382 tmpm380/m382 - 9 / 24 6.3 clock control 6.3.1 clock system block diagram fig. 6-1 shows the clock system diagram. each clock is defined as follows. fosc1 : clock input from external high-speed oscillator (x1 and x2) fosc2 : clock input from internal high-speed oscillator fs : clock input from external low-speed oscillator (xt1 and xt2) fosc : high-speed clock specified by cgosccr 6 clock/mode control tmpm380/m382 tmpm380/m382 - 10 / 24 - fosc fpll fsys fs ? high-speed oscillator1 x1 x2 cgosccr tmpm380/m382 tmpm380/m382 - 11 / 24 6.3.3 clock multiplication circuit (pll) this circuit outputs the fpll clock that is quadruple of the high-speed oscillator ou tput clock, fosc. this lowers the oscillator input frequency whil e increasing the internal clock speed. the pll is disabled after reset is released. to enable the pll, set "1" to the cgosccr 6 clock/mode control tmpm380/m382 tmpm380/m382 - 12 / 24 - the following are the examples of the warm-up function configuration. tmpm380/m382 tmpm380/m382 - 13 / 24 6.3.5 system clock the tmpm380 offers three selectable system clocks : two high-speed clocks and one low-speed clock. two kinds of high-speed clocks are selectable either internal oscillator or exter nal oscillator. after reset, internal oscillator is available, and external osc illator is stop. the high-speed clocks are dividable. 6.3.5.1 high speed clock ? input frequ ency from high-speed oscillator1 (x1 and x2) : 8mhz to 10mhz ? input frequency from high-speed osc illator2 (internal oscillator) : 10mhz ? clock gear:1/1, 1/2, 1/4, 1/8, 1/16 (after reset: 1/1) table 6-2 range of high-frequency (unit:mhz) clock gear (pll=on) clock gear (pll=off) input frequency min. operating freq. max. operating freq. after reset (pll=off, cg=1/1) 1/1 1/2 1/4 1/8 1/16 1/ 1 1/2 1/4 1/8 1/16 8mhz 8mhz 32 16 8 4 2 8 4 2 1 ** osc1 10mhz 10mhz 40 20 10 5 2.5 10 5 2.5 1.25 ** osc2 10mhz 1mhz 40mhz 10mhz 40 20 10 5 2.5 10 5 2.5 1.25 ** (note1) (note2) (note3) (note4) pll=on/off setting: availa ble in cgosccr 6 clock/mode control tmpm380/m382 tmpm380/m382 - 14 / 24 - 6.3.5.2 low speed clock ? input frequ ency from xt1 and xt2 table 6-3 range of low frequency input frequency range maximum operating frequency minimum operating frequency 30 to 34(khz) 34 khz 30 khz 6.3.6 prescaler clock control each peripheral function has a prescaler for dividing a clock. as the clock t0 to be input to each prescaler, the "fperiph" clock specified in t he cgsyscr tmpm380/m382 tmpm380/m382 - 15 / 24 6.4 modes and mode transitions 6.4.1 mode transitions the normal mode and the slow mode use the high- speed and low-speed clocks for system clock respectively. the idle, sleep and stop modes can be used as the low power consumption mode that enables to reduce power consumption by halting processor core operation. when the low-speed clock is not used, the slow and sleep modes cannot be used. fig. 6-2 shows a mode transition diagram for a de scri ption of sleep-on-exit, refer to ?cortex-m3 technical reference manual?. idle mode reset reset release instruction / slee p on exit stop mode slow mode sleep mode interru p t instruction / slee p on exit interru p t interru p t instruction / slee p on exit instruction / slee p on exit interru p t interru p t instruction / slee p on exit instruction normal mode (fosc) -6:* ? ?-: ? fig. 6-2 mode transition diagram 6 clock/mode control tmpm380/m382 tmpm380/m382 - 16 / 24 - 6.5 operation modes two operation modes, normal and slow, are avail able. the features of each mode are described below. 6.5.1 normal mode this mode is to operate the cpu core and the peripheral hardware by using the high-speed clock(fosc1 or fosc2). it is shifted to the normal mode with fosc2(internal high-speed oscillator) after reset. also low-speed clock is possible to use. 6.5.2 slow mode this mode is to operate the cpu core and the periph eral hardware by using the low-speed clock with high-speed clock stopped. the slow mode reduces power consumption compared to the normal mode. this mode allows only the following peripheral func tions to operate: i/o ports, real-time clock (rtc), tmrb, mpt(tmrb mode), remote co ntrol signal preprocessor (rmc). (note1) (note2) be sure to stop peripheral functions except for the cpu, rtc, i/o ports, tmrb, mpt(tmrb mode) and rmc before switching to the slow mode. in the slow mode, be sure not to perform reset using the application interrupt and reset control register tmpm380/m382 tmpm380/m382 - 17 / 24 6.5.4 idle mode only the cpu is stopped in this mode. each peripheral function has one bit in its control register for enabling or disabling operation in the idle mode. when the idle mode is entered, perip heral functions for whic h operation in the idle mode is disabled stop operation and hold the state at that time. the following peripheral functions can be enabled or disabled in the idle mode. for setting details, see the chapter on each peripheral function. y 16-bit timer/event counter (tmrb) y 16-bit multi purpose timer counter (mpt : except pmd function) y serial channel (sio) y serial bus interface (sbi) y ad converter (adc) y watchdog timer (wdt) y pll 6.5.5 sleep mode the internal low-speed oscillator, real time clock and rmc can op erate. by releasing the sleep mode, the device returns to the preceding mode of the sleep mode and starts operation. (note) when pb4 is configured as a debug function pin, it prevents the low power consumption mode from being fully effective. configure pb4 to function as a general-purpose port if the debug function is not used. 6.5.6 stop mode all the internal circuits including the in ternal oscillator are brought to a stop. by releasing the stop mode, the device return s to the preceding mode of the stop mode and starts operation. the stop mode enables to select the pin status by setting the cgstbycr 6 clock/mode control tmpm380/m382 tmpm380/m382 - 18 / 24 - table 6-5 pin states in stop mode pin name i/o tmpm380/m382 tmpm380/m382 - 19 / 24 6.5.8 operational state in each mode table 6-7 sh ow the op erational state in each mode. for i/o port, ? ? and ?? indicate that input/output is enabled and disabled respectively. for other functions, ? ? and ?? indicate that clock is supplied and is not supplied respectively. table 6-7 operational state in each mode block normal slow idle sleep stop processor core i/o port * (note 3) ssp (note 1) adc (note 1) sio (note 1) (note 1) (note 1) sbi (note 1) (note 1) (note 1) wdt (note 1) (note 1) (note 1) tmrb (note 1) (note 1) mpt(tmrb mode) (note 1) (note 1) mpt(igbt mode) (note 1) on/off selectable for each module (note 1) (note 1) mpt(pmd mode) (note 1) (note 1) (note 1) rmc rtc cg pll ofd (note 4) (note 4) high-speed oscillator (fosc1) (note 2) high-speed oscillator (fosc2) (note 2) low-speed oscillator (fs) : operating, : stopped (note 1) in the slow mode, the adc, sio, sbi, ssp, mpt(igbt,pmd) and wdt cannot be used and must be stopped before switch to slow mode. (note 2) the high-speed oscillator(1 or 2) does not stop automatically in slow mode and must be stopped by setting cgosccr1 6 clock/mode control tmpm380/m382 tmpm380/m382 - 20 / 24 - 6.5.9 releasing the low power consumption mode the low power consumption mode can be released by an interrupt request, nmi or reset. the release source that can be used is determined by the low power consumption mode selected. details are shown in table 6-8 . t able 6-8 re lease source in each mode low power consumption mode idle sleep stop interrupt int0~f (note 1) intrtc intrmcrx intssp0,1 intsbi0,1 intrx0 to 4,/ inttx0 to 4 intadpd0,1/ intadcp0,1 intadtmr/ intadsft intpmd0,1/ intemg0,1 intmttb00 to 20 intmttb01 to 21 intmtcap00 to 20, 01,to 21 intmtemg0,1,2 inttb00 to 70,01 to 71 intcap00 to 70, 01 to 71 intenc0,1 intdmacerr/ intdmactc nmi (intwdt) nmi (intvltd) release source reset (reset pin and por) : starts the interrupt handling after the mode is released. (the reset initializes the lsi). : unavailable (note 1) to release the low power consumption mode by using the level mode interrupt, keep the level until the interrupt handling is started. changing the level before then will prevent the interrupt handling from starting properly. (note 2) for switching to the low power consumption mode, set the cpu to prohibit all the interrupts other than the release source. if not, releasing may be executed by an unspecified interrupt. release by interrupt request to release the low power consumption mode by an interrupt, the cpu must be set in advance to detect the interrupt. in addition to the setting in t he cpu, the clock generator must be set to detect the interrupt to be used to release the sleep and stop modes. release by nmi there are two kinds of nmi sources: wdt inte rrupt (intwdt) and vltd interrupt (intvltd). intwdt can be used in idle mode only. tmpm380/m382 tmpm380/m382 - 21 / 24 release by reset any low power consumption modes can be released by reset from the reset pin. after that, the mode switches to normal and all the registers are initialized as is the case with normal reset. refer to section of ?interrupts" for details. 6 clock/mode control tmpm380/m382 tmpm380/m382 - 22 / 24 - 6.5.10 warm-up mode transition requires the warm-up so that the oscillator provides stable oscillation. in the mode transition from stop to normal/ slow or from sleep to normal, the warm-up counter is activated automatically. and then the syst em clock output is started after the elapse of configured warm-up time. it is necessary to sele ct the oscillator to be used for warm-up in the cgosccr tmpm380/m382 tmpm380/m382 - 23 / 24 6.5.11 clock operations in mode transition the clock operations in mode transition are described in the following sections. 6.5.11.1 transition of operation modes: normal st op nor mal before entering to stop mode, please set warm ing-up time to cgosccr< wuodr[13:0]> and select clock-source that is same as 6 clock/mode control tmpm380/m382 tmpm380/m382 - 24 / 24 - 6.5.11.3 transition of operation modes: slow stop slow the warm-up is activated automatica lly. it is necessary to set the wa rm-up time before entering the stop mode. 6.5.11.4 transition of operation modes: slow sleepslow the lo w-sp eed clock continues oscillation in the sleep mode. there is no need to make a warm-up setting. slow slow stop mode warm-up completes. system clock starts. ? fsys (system clock = fs) fs warm-u p low-speed clock starts oscillating. warm-up starts. ? system clock stops wfi instruction / sleep-on-exit ? release event occurs. ? slow slow sleep mode fsys (system clock = fs) fs system clock stops wfi instruction / slee p -on- exit release event occurs. ? system clock starts. ? ? tmpm380/m382 tmpm380/m382 - 1 / 59 - 7 exceptions this chapter describes features, types and handling of exceptions. exceptions have close relation to the cpu core. re fer to ?cortex-m3 technical reference manual? if needed. 7.1 overview an exception causes the cpu to stop the current ly executing process a nd handle another process. there are two types of exceptions: those that are generated when so me error condition occurs or when an instruction to generate an exception is executed; and those that are generated by hardware, such as an interrupt request signal from an external pin or peripheral function. all exceptions are handled by the nested vectored inte rrupt controller (nvic) in the cpu according to the respective priority levels. when an exception oc curs, the cpu stores the cu rrent state to the stack and branches to the corresponding in terrupt service routine (isr). upon completion of the isr, the information stored to the stac k is automatically restored. 7.1.1 exception types the following types of exceptio ns exist in the cortex-m3. for detailed descriptions on each exception, refe r to ?cortex-m3 technical reference manual?. z reset z non-maskable interrupt (nmi) z hard fault z memory management z bus fault z usage fault z svcall (supervisor call) z debug monitor z pendsv z systick z external interrupt 7 exceptions tmpm380/m382 tmpm380/m382 - 2 / 59 - 7.1.2 handling flowchart the following shows how an exception/interrupt is handled. indicates hardware handling. indicates software handling. each step is described later in this chapter. processing description see detection by cg/cpu the cg/cpu detects the exception request. section 7.1.2.1 handling by cpu the cpu handles the exception request. branch to isr the cpu branches to the corresponding interrupt service routine (isr). section 7.1.2.2 execution of isr necessary processing is executed section 7.1.2.3 return from exception the cpu branches to another isr or returns to the previous program. section 7.1.2.4 tmpm380/m382 tmpm380/m382 - 3 / 59 - 7.1.2.1 exception request and detection (1) exception oc currence exception source s inclu de instruct ion execution by the cpu, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. an exception by cpu instruction execution is caused when the cp u executes an instruction that generate an exception or when an error condi tion occurs during instruction execution. an exception also occurs by an instruction fetch from the execute never (xn) region or an access violation to the fault region. an interrupt is generated from an external interrupt pi n or peripheral function. for interrupts that are used for releasing a standby mode, relevant settings must be made in the clock generator. for details, refer to ?7.5 interrupts?. (2) exception detection if multiple exceptions occur simu lt a neo usly, the cpu takes the exception with the highest priority. table 7-1 shows the priority of exceptions. ?configurabl e? means that it is possible to assign a priority level to that exception. memory management, bus fault and usage fault exceptions can be enabled or disabled. if a disabled exception occurs, it is handled as hard fault. 7 exceptions tmpm380/m382 tmpm380/m382 - 4 / 59 - table 7-1 exception types and priority no exception type priority description reset -3 (highest) reset pin, wdt or sysretreq 2 non-maskable interrupt -2 wdt or vltd 3 hard fault -1 fault that cannot activate because a higher-priority fault is being handled or it is disabled 4 memory management configurable exception from the memory protection unit (mpu) (note 1) instruction fetch from the execute never (xn) region 5 bus fault configurable access violation to the hard fault region of the memory map 6 usage fault configurable undefined instruction execution or other faults related to instruction execution 7-10 reserved 11 svcall configurable system service call with svc instruction 12 debug monitor configurable debug monitor when the core is not halting 13 reserved 14 pendsv configurable pendable system service request 15 systick configurable notification from system timer 16- external interrupt configurable external interrupt pin or peripheral function (note 2) (note 1) this product does not contain the mpu (note 2) external interrupts have different sources and numbers in each product. for details, see ? 7.5.1.4 list of interrupt factors?. (3) priority setting use the interrupt priority registers to assign a priority to each of the ex ternal interrupts. the priority of other exceptions can be set in the system handler priority registers. the priority registers are configurabl e, allowing the number of bits for setting priority levels to vary between three to eight bits. therefore, the range of priority levels that can be assigned vary with each product. in case of eight bits, a priority level can be set from 0 to 255. priority level 0 is the highest priority level. in case of the same priority level to multiple exceptions, the lowest- numbered exception has the highest priority. (note) in this product, three bits are used for assigning a priority level in the interrupt priority registers and system handler priority registers. tmpm380/m382 tmpm380/m382 - 5 / 59 - 7.1.2.2 exception handling and branch to the in terrupt service routin e (pre-em ption) when an exception occurs, the cpu suspends the currently executing proc ess and branches to the interrupt service routine. this is called ?pre-emption?. (1) stacking when the cpu detects an exception, it pushes the contents of the foll owing eight registers to the stack in the following order: ? program counter (pc) ? program status register (xpsr) ? r0 - r3 ? r12 ? link register (lr) the sp is decremented by eight words by the comp letion of the stack push. the following shows the state of the stack after the regi ster contents have been pushed. old sp sp (2) fetching an isr at the same time as p u shin g the register contents to the stack, the cpu executes an instruction to fetch an isr. prepare a vector table containing the top addresses of isrs for each exception. after reset, the vector table is located at address 0x0000_0000 in the code space. by setting the vector table offset register, it is possible to place the vector table at any address in the code or sram space. the vector table should also contain the initial value of the main stack. 7 exceptions tmpm380/m382 tmpm380/m382 - 6 / 59 - (3) late-arriving if the cpu detect s a hi gher priority exception before executing the isr for a pr evious exception, the cpu handles the higher priority exception first. this is called ?late-arriving?. a late-arriving exception causes the cpu to fetch a new vector address for branching to the corresponding isr, but the cpu does not newly push the register contents to the stack. (4) vector table the vecto r t able is configured as shown below. it must always be set the first four words (stack top address, reset isr address, nmi isr address, and hard fault isr address) . isr addresses for other exceptions are prepared in case if necessary. offset exception contents setting 0x00 reset initial value of the main stack required 0x04 reset isr address required 0x08 non-maskable interrupt isr address required 0x0c hard fault isr address required 0x10 memory management isr address optional 0x14 bus fault isr address optional 0x18 usage fault isr address optional 0x1c 0x28 reserved 0x2c svcall isr address optional 0x30 debug monitor isr address optional 0x34 reserved 0x38 pendsv isr address optional 0x3c systick isr address optional 0x40 external interrupt isr address optional tmpm380/m382 tmpm380/m382 - 7 / 59 - 7.1.2.3 executing an isr an isr performs ne cessary processin g for the co rresponding exception. isrs must be prepared by the user. an isr may need to include code for clearing the interr upt request so that the same interrupt will not occur again upon return to normal program execution. for details about interrupt handling, see ? 7.5 interrupt ?. if a higher pri o rity exception occu rs during isr execution for the cu rrent exception, the cpu abandons the currently executing isr and services the newl y detected exception. 7.1.2.4 exception exit (1) execution af t er returning from an isr when retu rni ng from an isr, the cpu takes one of the following actions: z tail-chaining if a pending exception exists and there are no stac ked exceptions or the pending exception has higher priority than all stacked exceptions, the cp u returns to the isr of the pending exception. in this case, the cpu skips the pop of eight registers and push of eight registers when exiting one isr and entering another. this is called ?tail-chaining?. z returning to the last stacked isr if there are no pending exceptions or if the highest priority stacked exception is higher priority than the highest priority pending exception, the cpu returns to the last stacked isr. z returning to the previous program if there are no pending or stacked exceptions, the cpu returns to the previous program. 7 exceptions tmpm380/m382 tmpm380/m382 - 8 / 59 - (2) exception exit sequence when retu rning from an isr, the cp u performs the following operations: z pop eight registers pops the eight registers (pc, xpsr, r0 to r3 , r12 and lr) from the stack and adjust the sp. z load current active interrupt number loads the current active interrupt number from t he stacked xpsr. the cpu uses this to track which interrupt to return to. z select sp if returning to an exception (handler mode), sp is sp_main. if returning to thread mode, sp can be sp_main or sp_process. tmpm380/m382 tmpm380/m382 - 9 / 59 - 7.2 reset exceptions reset exceptions are generated from the following three sources. use the reset flag (cgrstflg) register of the cl ock generator to identify the source of a reset. ? external reset pin a reset exception occurs when an external reset pin changes from ?l? to ?h?. ? reset exception by por a reset exception occurs when the power is turn ed on. for details, see the chapter on the por. ? reset exception by wdt the watchdog timer (wdt) has a reset generating f eature. for details, see the chapter on the wdt. ? reset exception by ofd the oscillation frequency detection (ofd) has a rese t generating feature. for details, see the chapter on the ofd. ? reset exception by sysresetreq a reset can be generated by setting the sysresetreq bit in the nvic?s application interrupt and reset control register. 7.3 non-maskable interrupts (nmis) non-maskable interrupts are generated from the following two sources. use the nmi flag (cgnmiflg) register of the clock generator to identify the source of a non-maskable interrupt. ? non-maskable interrupt by wdt the watchdog timer (wdt) has a non-maskable in terrupt generating feat ure. for details, see the chapter on the wdt. ? non-maskable interrupt by vltd the voltage level detector (vltd) has a non-mask able interrupt generating feature. for details, see the chapter on the vltd. 7 exceptions tmpm380/m382 tmpm380/m382 - 10 / 59 - 7.4 systick systick provides interr upt features using the cpu?s system timer. in case set a value in the systick reload value register and enable the systick features in the systick control and status register, the counter loads with the value set in the reload value register and begins counting down. when the counter reaches ?0?, a systick exception occurs. it is also possible to pend exceptions and use a flag to know when the timer reaches ?0?. the systick calibration value register holds a reload value for counting 10 ms with the system timer. the count clock frequency varies with each product, and so the value set in the systick calibration value register also varies with each product. (note) in this product, the system timer counts based on a clock obtained by dividing the clock input from the x1 pin by 32. the systick calibration value register is set to 0x9c4, which provides 10 ms timing when the clock input from x1 is 8 mhz. in case of 10mhz clock input, 10 ms timing is made by setting 0xc35 to systick reload register. tmpm380/m382 tmpm380/m382 - 11 / 59 - 7.5 interrupt this chapter describes routes, factors and required settings of interrupts. the cpu is notified of interrupts by each signal of in terrupt factor. it sets priority on the interrupts and handles an interrupt request with the highest priority. the cpu is notified of the interrupt factor, which is used for clearing the standby modes, via a clock generator. therefore setting of the clock generator is required. 7.5.1 interrupt factors 7.5.1.1 interrupt route fig 7-1 shows an interrupt request route. fig 7-1 interrupt route peripheral ? ? clock generator ? interrupt request clearing standby mode ? ? external interrupt p in port peripheral ? ? 7 exceptions tmpm380/m382 tmpm380/m382 - 12 / 59 - 7.5.1.2 interrupt signal generation an interrupt request signal is generated from an ex ternal pin assigned as the interrupt factor or a peripheral ip. ? from external pin set the port control register so that the external pin can perform as an interrupt function pin. ? from peripheral ip set the peripheral ip to make it possible to output the interrupt. see chapters of relevant ip for details. 7.5.1.3 transmission of interrupt signal an interrupt si gnal from an external pin or a peripheral ip is directly sent to t he cpu unless it is used to clear the standby mode. an interrupt that can be used to clear the stand by mode is transmitted to the cpu via the clock generator. therefore, it is necessary to set the clock generator in advanc e. an interrupt from an external pin can be used without setting the clock generator if it does not function as the clearing standby factor. tmpm380/m382 tmpm380/m382 - 13 / 59 - 7.5.1.4 list of interrupt factors table 7-2 shows the list of interru pt factors. t able 7-2 list of hardware interrupt factors (1/2) int no. interrupt factors active level (clearing standby) cg interrupt mode control register 0 int0 interrupt pin (ph0/ain0/int0) 1 int1 interrupt pin (ph1/ain1/int1) 2 int2 interrupt pin (ph2/ain2/int2) 3 int3 interrupt pin (pa0/tb0in/int3) cgimcga 4 int4 interrupt pin (pa2/tb1in/int4) 5 int5 interrupt pin (pe4/tb2in//int5) high/low edge/level selectable cgimcgb 6 intrx0 serial reception (channel.0) 7 inttx0 serial transmit (channel.0) 8 intrx1 serial reception (channel.1) 9 inttx1 serial transmit (channel.1) 10 intssp0 syncronous serial port 0 11 intssp1 syncronous serial port 1 (note1) 12 intemg0 pmd0 emg interrupt (mpt0) 13 intemg1 pmd1 emg interrupt (mpt1) (note1) 14 intsbi0 serial bus interface 0 interrupt 15 intsbi1 serial bus interface 1 interrupt (note1) 16 intadpd0 adc conversion triggered by pmd0 is finished 17 intrtc realtime clock interrupt low edge cgimcge 18 intadpd1 adc conversion tri ggered by pmd1 is finished 19 intrmcrx remote controller reception interrupt high edge cgimcge 20 inttb00 16bit tmrb0 compare matc h detection 0/ over flow 21 inttb01 16bit tmrb0 compare match detection 1 22 inttb10 16bit tmrb1 compare matc h detection 0/ over flow 23 inttb11 16bit tmrb1 compare match detection 1 24 inttb40 16bit tmrb4 compare matc h detection 0/ over flow 25 inttb41 16bit tmrb4 compare match detection 1 26 inttb50 16bit tmrb5 compare match detection 0/ over flow 27 inttb51 16bit tmrb5 compare match detection 1 28 intpmd0 pmd0 pwm interrupt (mpt0) 29 intpmd1 pmd1 pwm interrupt (mpt1) (note1) 30 intcap00 16bit tmrb0 input capture 0 31 intcap01 16bit tmrb0 input capture 1 32 intcap10 16bit tmrb1 input capture 0 33 intcap11 16bit tmrb1 input capture 1 34 intcap40 16bit tmrb4 input capture 0 35 intcap41 16bit tmrb4 input capture 1 36 intcap50 16bit tmrb5 input capture 0 37 intcap51 16bit tmrb5 input capture 1 38 int6 interrupt pin (pe6/tb3in/int6) (note1) 39 int7 interrupt pin (pe7/tb3out/int7) (note1) high/low edge/level selectable cgimcgb 40 intrx2 serial reception (channel.2) (note1) 41 inttx2 serial transmi t (channel.2) (note1) 42 intadcp0 adc conversion moni toring function interrupt 0 43 intadcp1 adc conversion moni toring function interrupt 1 44 intrx4 serial reception (channel.4) (note1) 45 inttx4 serial transmi t (channel.4) (note1) 7 exceptions tmpm380/m382 tmpm380/m382 - 14 / 59 - table 7-2 list of hardware interrupt factors (2/2) no. interrupt factors active trigger (clearing standby) cg interrupt mode control register 46 inttb20 16bit tmrb2 compare matc h detection 0/ over flow 47 inttb21 16bit tmrb2 compare match detection 1 48 inttb30 16bit tmrb3 compare matc h detection 0/ over flow 49 inttb31 16bit tmrb3 compare match detection 1 50 intcap20 16bit tmrb2 input capture 0 51 intcap21 16bit tmrb2 input capture 1 52 intcap30 16bit tmrb3 input capture 0 53 intcap31 16bit tmrb3 input capture 1 54 intadsft adc conversion started by software is finished 55 reserved reserved 56 intadtmr adc conversion triggered by timer is finished 57 reserved reserved 58 int8 interrupt pin (pa7/tb4in/int8) 59 int9 interrupt pin (pd3/int9) (note1) 60 inta interrupt pin (pj6/ain6/inta) (note1) 61 intb interrupt pin (pj7/ain7/intb) (note1) high/low edge/level selectable cgimcgc 62 intenc0 encoder input0 interrupt (note1) 63 intenc1 encoder input1 interrupt (note1) 64 intrx3 serial reception (channel.3) (note1) 65 inttx3 serial transmit (channel.3) (note1) 66 inttb60 16bit tmrb6 compare match detection 0 / over flow 67 inttb61 16bit tmrb6 compare match detection 1 68 inttb70 16bit tmrb7 compare match detection 0 / over flow 69 inttb71 16bit tmrb7 compare match detection 1 70 intcap60 16bit tmrb6 input capture 0 71 intcap61 16bit tmrb6 input capture 1 72 intcap70 16bit tmrb7 input capture 0 73 intcap71 16bit tmrb7 input capture 1 74 intc interrupt pin (pd0/enca0/tb5in/intc) (note1) 75 intd interrupt pin (pd2/encz0/intd) (note1) 76 inte interrupt pin (pn7/mt2in/inte) (note1) 77 intf interrupt pin (pl2/intf) high/low edge/level selectable cgimcgd 78 intdmacerr dma transfer error 79 intdmactc dma end of transfer 80 intmttb00 16-bit mpt0 igbt period/ compare match detection 0/ over flow 81 intmttb01 16-bit mpt0 igbt trigger/ compare match detection 1 82 intmttb10 16-bit mpt1 igbt period/ compare match detection 0/ over flow (note1) 83 intmttb11 16-bit mpt1 igbt trigger/ compare match detection 1 (note1) 84 intmttb20 16-bit mpt2 igbt period/ compare match detection 0/ over flow (note1) 85 intmttb21 16-bit mpt2 igbt trigger/ compare match detection 1 (note1) 86 intmtcap00 16-bit mpt0 input capture 0 87 intmtcap01 16-bit mpt0 input capture 1 88 intmtcap10 16-bit mpt1 input capture 0 (note1) 89 intmtcap11 16-bit mpt1 input capture 1 (note1) 90 intmtcap20 16-bit mpt2 input capture 0 (note1) 91 intmtcap21 16-bit mpt2 input capture 1 (note1) 92 intmtemg0 16-bit mpt0 igbt emg interrupt 93 intmtemg1 16-bit mpt1 igbt emg interrupt (note1) 94 intmtemg2 16-bit mpt2 igbt emg interrupt (note1) note1 : for tmpm380 tmpm380/m382 tmpm380/m382 - 15 / 59 - 7.5.1.5 active level the active level indicate s which change in signal of an interrupt factor triggers an interrupt. the cpu recognize an interrupt signal as an interrupt factor w hen it is changed from ?l? to ?h?. a signal directly sent from the peripheral ip to the cpu is configur ed to output the ?h? pulse as an interrupt request. only interrupt request from external pin have the opt ion as the interrupt to clear the standby mode. the active level setting for clock generator is selectable from ?h? level, ?l? level, rising edge or falling edge. if the interrupt is used for clearing the standby mode, setting the clock generator register is required. i.e. enable the cgimcgx 7 exceptions tmpm380/m382 tmpm380/m382 - 16 / 59 - 7.5.2 interrupt handling 7.5.2.1 flowchart the follo wing sho ws how an interrupt is handled. indicates hardware handling. indicates software handling. processing details see settings for detection set the cpu register to detect an interrupt. set the clock generator as well if the interrupt clear the standby mode. common setting cpu register setting to clear standby mode clock generator 7.5.2.2 preparation settings for generating interrupt request signal execute an appropriate setting to generate the interrupt signal depending on the interrupt type. interrupt from the external pin port interrupt from peripheral ip peripheral ip (see chapters of relevant ip for details.) hardware interrupt factor is generated the hardware interrupt factor is generated. cg detects interrupt (factor to clear standby mode) the interrupt, which is used for clearing the standby modes, is connected to the cpu via the clock generator. 7.5.2.3 detection by cg clearing standby mode not clearing standby mode tmpm380/m382 tmpm380/m382 - 17 / 59 - processing details see detecting interrupt the cpu detects the interrupt. in case several interrupt fact or are detected, the interrupt factor with the highest priority is selected according to the priority order. 7.5.2.4 dete ction by cpu handling interrupt the cpu handles the interrupt. the cpu pushes resister c ontents to the stack before entering the interrupt service routine 7.5.2.5 cpu pr oc essing executing interrupt service routine program for the interrupt service routine. clear the interrupt factor if needed. returning to preceding program configure to return to the preceding program from the interrupt service routine. 7.5.2.6 interrupt se rv ice routin e 7 exceptions tmpm380/m382 tmpm380/m382 - 18 / 59 - 7.5.2.2 preparation when pre paring for an interrupt, it is needed to pay att ention to the order of co nfiguration to avoid any unexpected interrupt on the way. initiating an interrupt or changing its configuration must be implemented in the following order basically. disable the interrupt by the cpu. configure from the farthest route from the cpu. then enable the interrupt by the cpu. in order not to generate unnecessary interrupt after condition setting, in case of setting the clock generator, it need to clear the interrupt related dat a in the clock generator before enable the interrupt. the following shows the order of interrupt handling and describe how to configure them. (1) disabling interrupt by cpu (2) cpu registers setting (3) preconfiguration 1 (inter rupt from external pin) (4) preconfiguration 2 (interrupt from peripheral ip) (5) configuring the clock generator (6) enabling interrupt by cpu (1) disabling interrupt by cpu t o make th e cpu for not accepting any interrupt, write ?1? to the corresponding bit of the interrupt clear-enable register. each bit of the register, of whic h default setting is ?0? with interrupt disabled, is assigned to single interrupt factor. cpu register interrupt clear-enable tmpm380/m382 tmpm380/m382 - 19 / 59 - (3) preconfiguration 1 (interru pt from external pin) set ?1? to the port function register of the corre sponding pin. setting pnfrx[m] allows the pin to be used as the function pin. setting pnie[m] a llows the pin to be used as the input port. port register pnfrx 7 exceptions tmpm380/m382 tmpm380/m382 - 20 / 59 - (6) enabling interrupt by cpu enable the inte rrupt by the cpu a s shown below. it is possible to clear the suspended interrupt by writing the interrupt clear -pending register. then, enable the intended interrupt with the interrupt set-enable register. each bit of the register is assigned to each interrupt factor. writing ?1? to the corresponding bit of the clear -pending register clears the suspended interrupt. writing ?1? to the corresponding bit of the set- enable register enables the intended interrupt. cpu register interrupt clear-pending tmpm380/m382 tmpm380/m382 - 21 / 59 - 7.5.2.6 interrupt service routine interrupt service ro utine requires specific progra mming according to the application to be used. this section describes what is reco mmended at the service routine programming and how the factor is cleared. (1) pushing during interrupt service routine common interru pt service routine is accompanied wi th the interrupt handling and the pushing of the register contents. the cortex-m3 core automatically pushes the contents of pc, psr, r0-r3, r12 and lr to the stack. no extra programming is required for them. push the contents of other registers if needed. an interrupt with the higher priority and faults such as nmi are accepted even when the interrupt service routine is being executed. therefore, it is recommend to push t he contents of the general purpose register that might be rewritten. (2) clearing interrupt factor as for an interrupt factor clea rin g the standby mo de, it need to clear the interrupt request with the cgicrcg register of the clock generator. if ?h? or ?l? level signal is specified as the trigger to enter the active state, the factor is held unless it is cleared. in this case, the factor needs to be cleared. clearing the factor causes clearing the interrupt request signal from clock generator. if a rising or falling edge is specified as the trigger to enter the active state, the factor is cleared by setting the value which corresponds to the interrupt, to the cgicrcg register. the factor is detected again when the specified edge appears again. 7 exceptions tmpm380/m382 tmpm380/m382 - 22 / 59 - 7.6 exception/interrupt-related registers the clock generator regi sters and their addresses are as shown below. 7.6.1 register list nvic resisters systick control and stat us resister 0xe000_e010 systick reload value resister 0xe000_e014 systick current value resister 0xe000_e018 systick calibration value register 0xe000_e01c interrupt set-enable register 1 0xe000_e100 interrupt set-enable register 2 0xe000_e104 interrupt set-enable register 3 0xe000_e108 interrupt clear-enable register 1 0xe000_e180 interrupt clear-enable register 2 0xe000_e184 interrupt clear-enable register 3 0xe000_e188 interrupt set-pending register 1 0xe000_e200 interrupt set-pending register 2 0xe000_e204 interrupt set-pending register 3 0xe000_e208 interrupt clear-pending register 1 0xe000_e280 interrupt clear-pending register 2 0xe000_e284 interrupt clear-pending register 3 0xe000_e288 interrupt priority register 0xe000_e400 - 0xe000_e45c vector table offset register 0xe000_ed08 system handler priority register 0xe000_ed18,0xe000_e d1c,0xe000_ed20 system handler control and state register 0xe000_ed24 clock generator registers cgicrcg cg interrupt request clear register 0x4004_0214 cgnmiflg nmi flag register 0x4004_0218 cgrstflg reset flag register 0x4004_021c cgimcga cg interrupt mode control register a 0x4004_0220 cgimcgb cg interrupt mode control register b 0x4004_0224 cgimcgc cg interrupt mode control register c 0x4004_0228 cgimcgd cg interrupt mode control register d 0x4004_022c cgimcge cg interrupt mode control register e 0x4004_0230 tmpm380/m382 tmpm380/m382 - 23 / 59 - 7.6.2 nvic registers 7.6.2.1 systick control and status register 7 6 5 4 3 2 1 0 bit symbol clk source tickint enable read/write r r/w r/w r/w after reset 0 0 0 0 function ?0? is read. 0: external reference clock 1: core clock 0: do not pend systick 1: pend systick 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 function ?0? is read. 23 22 21 20 19 18 17 16 bit symbol count flag read/write r r/w after reset 0 0 function ?0? is read. 0: timer not counted to 0 1: timer counted to 0 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function ?0? is read. 7 exceptions tmpm380/m382 tmpm380/m382 - 24 / 59 - 7.6.2.2 systick reload value register 7 6 5 4 3 2 1 0 bit symbol reload read/write r/w after reset undefined function reload value 15 14 13 12 11 10 9 8 bit symbol reload read/write r/w after reset undefined function reload value 23 22 21 20 19 18 17 16 bit symbol reload read/write r/w after reset undefined function reload value 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function ?0? is read. tmpm380/m382 tmpm380/m382 - 25 / 59 - 7.6.2.3 systick current value register 7 6 5 4 3 2 1 0 bit symbol current read/write r/w after reset undefined function [read] current systick timer value [write] clear 15 14 13 12 11 10 9 8 bit symbol current read/write r/w after reset undefined function [read] current systick timer value [write] clear 23 22 21 20 19 18 17 16 bit symbol current read/write r/w after reset undefined function [read] current systick timer value [write] clear 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function ?0? is read. 7 exceptions tmpm380/m382 tmpm380/m382 - 26 / 59 - 7.6.2.4 systick calibration value register 7 6 5 4 3 2 1 0 bit symbol tenms read/write r after reset 1 1 0 0 0 1 0 0 function calibration value (note) 15 14 13 12 11 10 9 8 bit symbol tenms read/write r after reset 0 0 0 0 1 0 0 1 function calibration value (note) 23 22 21 20 19 18 17 16 bit symbol tenms read/write r after reset 0 0 0 0 0 0 0 0 function calibration value (note) 31 30 29 28 27 26 25 24 bit symbol noref skew read/write r r r after reset 0 0 0 function 0: reference clock provided 1: no reference clock 0: calibration value is 10 ms. 1: calibration value is not 10 ms. ?0? is read. tmpm380/m382 tmpm380/m382 - 27 / 59 - 7.6.2.5 interrupt set-enable register 1 7 6 5 4 3 2 1 0 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 7 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 6 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 5 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 4 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 3 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 2 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 1 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 0 [write] 1: enable [read] 0: disabled 1: enabled 15 14 13 12 11 10 9 8 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 15 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 14 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 13 [write] 1: enable [read] 0 disabled 1: enabled interrupt number 12 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 11 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 10 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 9 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 8 [write] 1: enable [read] 0: disabled 1: enabled 23 22 21 20 19 18 17 16 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 23 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 22 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 21 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 20 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 19 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 18 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 17 [write] 1: enable [read] 0: disabled 1: enabled interrupt number16 [write] 1: enable [read] 0: disabled 1: enabled 31 30 29 28 27 26 25 24 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 31 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 30 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 29 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 28 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 27 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 26 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 25 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 24 [write] 1: enable [read] 0: disabled 1: enabled 7 exceptions tmpm380/m382 tmpm380/m382 - 28 / 59 - ? 7.6.2.6 interrupt set-enable register 2 7 6 5 4 3 2 1 0 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 39 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 38 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 37 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 36 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 35 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 34 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 33 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 32 [write] 1: enable [read] 0: disabled 1: enabled 15 14 13 12 11 10 9 8 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 47 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 46 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 45 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 44 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 43 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 42 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 41 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 40 [write] 1: enable [read] 0: disabled 1: enabled 23 22 21 20 19 18 17 16 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 55 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 54 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 53 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 52 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 51 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 50 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 49 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 48 [write] 1: enable [read] 0: disabled 1: enabled 31 30 29 28 27 26 25 24 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 63 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 62 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 61 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 60 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 59 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 58 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 57 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 56 [write] 1: enable [read] 0: disabled 1: enabled tmpm380/m382 tmpm380/m382 - 29 / 59 - 7.6.2.7 interrupt set-enable register 3 ? 7 6 5 4 3 2 1 0 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 71 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 70 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 69 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 68 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 67 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 66 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 65 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 64 [write] 1: enable [read] 0: disabled 1: enabled 15 14 13 12 11 10 9 8 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 79 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 78 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 77 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 76 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 75 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 74 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 73 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 72 [write] 1: enable [read] 0: disabled 1: enabled 23 22 21 20 19 18 17 16 bit symbol setena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 87 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 86 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 85 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 84 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 83 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 82 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 81 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 80 [write] 1: enable [read] 0: disabled 1: enabled 31 30 29 28 27 26 25 24 bit symbol setena read/write r r/w after reset 0 0 0 0 0 0 0 0 function ?0? is read. interrupt number 94 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 93 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 92 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 91 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 90 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 89 [write] 1: enable [read] 0: disabled 1: enabled interrupt number 88 [write] 1: enable [read] 0: disabled 1: enabled 7 exceptions tmpm380/m382 tmpm380/m382 - 30 / 59 - 7.6.2.8 interrupt clear-enable register 1 ? 7 6 5 4 3 2 1 0 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 7 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 6 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 5 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 4 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 3 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 2 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 1 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 0 [write] 1: disable [read] 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 15 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 14 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 13 [write] 1: disable [read] 0: disabled 1 enabled interrupt number 12 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 11 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 10 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 9 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 8 [write] 1: disable [read] 0: disabled 1: enabled 23 22 21 20 19 18 17 16 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 23 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 22 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 21 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 20 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 19 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 18 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 17 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 16 [write] 1: disable [read] 0: disabled 1: enabled 31 30 29 28 27 26 25 24 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 31 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 30 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 29 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 28 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 27 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 26 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 25 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 24 [write] 1: disable [read] 0: disabled 1: enabled tmpm380/m382 tmpm380/m382 - 31 / 59 - 7.6.2.9 interrupt clear-enable register 2 ? 7 6 5 4 3 2 1 0 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 39 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 38 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 37 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 36 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 35 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 34 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 33 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 32 [write] 1: disable [read] 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 47 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 46 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 45 [write] 1: disable [read] 0: disabled 1 enabled interrupt number 44 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 43 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 42 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 41 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 40 [write] 1: disable [read] 0: disabled 1: enabled 23 22 21 20 19 18 17 16 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 55 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 54 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 53 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 52 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 51 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 50 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 49 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 48 [write] 1: disable [read] 0: disabled 1: enabled 31 30 29 28 27 26 25 24 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 63 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 62 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 61 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 60 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 59 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 58 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 57 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 56 [write] 1: disable [read] 0: disabled 1: enabled 7 exceptions tmpm380/m382 tmpm380/m382 - 32 / 59 - 7.6.2.10 interrupt clear-enable register 3 ? 7 6 5 4 3 2 1 0 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 71 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 70 [write] 1: disable [read] 0: disabled 1: enabled interrupt n umber 69 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 68 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 67 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 66 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 65 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 64 [write] 1: disable [read] 0: disabled 1: enabled 15 14 13 12 11 10 9 8 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt n umber 79 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 78 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 77 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 76 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 75 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 74 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 73 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 72 [write] 1: disable [read] 0: disabled 1: enabled 23 22 21 20 19 18 17 16 bit symbol clrena read/write r/w after reset 0 0 0 0 0 0 0 0 function interrupt number 87 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 86 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 85 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 84 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 83 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 82 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 81 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 80 [write] 1: disable [read] 0: disabled 1: enabled 31 30 29 28 27 26 25 24 bit symbol clrena read/write r r/w after reset 0 0 0 0 0 0 0 0 function ?0? is read. interrupt number 94 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 93 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 92 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 91 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 90 [write] 1: disable [read] 0: disabled 1: enabled interrupt n umber 89 [write] 1: disable [read] 0: disabled 1: enabled interrupt number 88 [write] 1: disable [read] 0: disabled 1: enabled tmpm380/m382 tmpm380/m382 - 33 / 59 - 7.6.2.11 interrupt set-pending register 1 ? 7 6 5 4 3 2 1 0 bit symbol setpend read/write r/w after reset undefined function interrupt number 7 [write] 1: pend [read] 0: not pending 1: pending interrupt number 6 [write] 1: pend [read] 0: not pending 1: pending interrupt number 5 [write] 1: pend [read] 0: not pending 1: pending interrupt number 4 [write] 1: pend [read] 0: not pending 1: pending interrupt number 3 [write] 1: pend [read] 0: not pending 1: pending interrupt number 2 [write] 1: pend [read] 0: not pending 1: pending interrupt number 1 [write] 1: pend [read] 0: not pending 1: pending interrupt number 0 [write] 1: pend [read] 0: not pending 1: pending 15 14 13 12 11 10 9 8 bit symbol setpend read/write r/w after reset undefined function interrupt number 15 [write] 1: pend [read] 0: not pending 1: pending interrupt number 14 [write] 1: pend [read] 0: not pending 1: pending interrupt number 13 [write] 1: pend [read] 0: not pending 1: pending interrupt number 12 [write] 1: pend [read] 0: not pending 1: pending interrupt number 11 [write] 1: pend [read] 0: not pending 1: pending interrupt number10 [write] 1: pend [read] 0: not pending 1: pending interrupt number 9 [write] 1: pend [read] 0: not pending 1: pending interrupt number 8 [write] 1: pend [read] 0: not pending 1: pending 23 22 21 20 19 18 17 16 bit symbol setpend read/write r/w after reset undefined function interrupt number 23 [write] 1: pend [read] 0: not pending 1: pending interrupt number 22 [write] 1: pend [read] 0: not pending 1: pending interrupt number 21 [write] 1: pend [read] 0: not pending 1: pending interrupt number 20 [write] 1: pend [read] 0: not pending 1: pending interrupt number 19 [write] 1: pend [read] 0: not pending 1: pending interrupt number 18 [write] 1: pend [read] 0: not pending 1: pending interrupt number 17 [write] 1: pend [read] 0: not pending 1: pending interrupt number 16 [write] 1: pend [read] 0: not pending 1: pending 31 30 29 28 27 26 25 24 bit symbol setpend read/write r/w after reset undefined function interrupt number 31 [write] 1: pend [read] 0: not pending 1: pending interrupt number 30 [write] 1: pend [read] 0: not pending 1: pending interrupt number 29 [write] 1: pend [read] 0: not pending 1: pending interrupt number 28 [write] 1: pend [read] 0: not pending 1: pending interrupt number 27 [write] 1: pend [read] 0: not pending 1: pending interrupt number 26 [write] 1: pend [read] 0: not pending 1: pending interrupt number 25 [write] 1: pend [read] 0: not pending 1: pending interrupt number 24 [write] 1: pend [read] 0: not pending 1: pending 7 exceptions tmpm380/m382 tmpm380/m382 - 34 / 59 - tmpm380/m382 tmpm380/m382 - 35 / 59 - 7.6.2.12 interrupt set-pending register 2 7 6 5 4 3 2 1 0 bit symbol setpend read/write r/w after reset undefined function interrupt number 39 [write] 1: pend [read] 0: not pending 1: pending interrupt number 38 [write] 1: pend [read] 0: not pending 1: pending interrupt number 37 [write] 1: pend [read] 0: not pending 1: pending interrupt number 36 [write] 1: pend [read] 0: not pending 1: pending interrupt number 35 [write] 1: pend [read] 0: not pending 1: pending interrupt number 34 [write] 1: pend [read] 0: not pending 1: pending interrupt number 33 [write] 1: pend [read] 0: not pending 1: pending interrupt number 32 [write] 1: pend [read] 0: not pending 1: pending 15 14 13 12 11 10 9 8 bit symbol setpend read/write r/w after reset undefined function interrupt number 47 [write] 1: pend [read] 0: not pending 1: pending interrupt number 46 [write] 1: pend [read] 0: not pending 1: pending interrupt number 45 [write] 1: pend [read] 0: not pending 1: pending interrupt number 44 [write] 1: pend [read] 0: not pending 1: pending interrupt number 43 [write] 1: pend [read] 0: not pending 1: pending interrupt number42 [write] 1: pend [read] 0: not pending 1: pending interrupt number 41 [write] 1: pend [read] 0: not pending 1: pending interrupt number40 [write] 1: pend [read] 0: not pending 1: pending 23 22 21 20 19 18 17 16 bit symbol setpend read/write r/w after reset undefined function interrupt number 55 [write] 1: pend [read] 0: not pending 1: pending interrupt number 54 [write] 1: pend [read] 0: not pending 1: pending interrupt number 53 [write] 1: pend [read] 0: not pending 1: pending interrupt number 52 [write] 1: pend [read] 0: not pending 1: pending interrupt number 51 [write] 1: pend [read] 0: not pending 1: pending interrupt number 50 [write] 1: pend [read] 0: not pending 1: pending interrupt number 49 [write] 1: pend [read] 0: not pending 1: pending interrupt number 48 [write] 1: pend [read] 0: not pending 1: pending 31 30 29 28 27 26 25 24 bit symbol setpend read/write r/w after reset undefined function interrupt number 63 [write] 1: pend [read] 0: not pending 1: pending interrupt number 62 [write] 1: pend [read] 0: not pending 1: pending interrupt number 61 [write] 1: pend [read] 0: not pending 1: pending interrupt number 60 [write] 1: pend [read] 0: not pending 1: pending interrupt number 59 [write] 1: pend [read] 0: not pending 1: pending interrupt number 58 [write] 1: pend [read] 0: not pending 1: pending interrupt number 57 [write] 1: pend [read] 0: not pending 1: pending interrupt number 56 [write] 1: pend [read] 0: not pending 1: pending 7 exceptions tmpm380/m382 tmpm380/m382 - 36 / 59 - tmpm380/m382 tmpm380/m382 - 37 / 59 - 7.6.2.13 interrupt set-pending register 3 7 6 5 4 3 2 1 0 bit symbol setpend read/write r/w after reset undefined function interrupt number 71 [write] 1: pend [read] 0: not pending 1: pending interrupt number 70 [write] 1: pend [read] 0: not pending 1: pending interrupt number 69 [write] 1: pend [read] 0: not pending 1: pending interrupt number 68 [write] 1: pend [read] 0: not pending 1: pending interrupt number 67 [write] 1: pend [read] 0: not pending 1: pending interrupt number 66 [write] 1: pend [read] 0: not pending 1: pending interrupt number 65 [write] 1: pend [read] 0: not pending 1: pending interrupt number 64 [write] 1: pend [read] 0: not pending 1: pending 15 14 13 12 11 10 9 8 bit symbol setpend read/write r/w after reset undefined function interrupt number 79 [write] 1: pend [read] 0: not pending 1: pending interrupt number 78 [write] 1: pend [read] 0: not pending 1: pending interrupt number 77 [write] 1: pend [read] 0: not pending 1: pending interrupt number 76 [write] 1: pend [read] 0: not pending 1: pending interrupt number 75 [write] 1: pend [read] 0: not pending 1: pending interrupt number 74 [write] 1: pend [read] 0: not pending 1: pending interrupt number 73 [write] 1: pend [read] 0: not pending 1: pending interrupt number 72 [write] 1: pend [read] 0: not pending 1: pending 23 22 21 20 19 18 17 16 bit symbol setpend read/write r/w after reset undefined function interrupt number 87 [write] 1: pend [read] 0: not pending 1: pending interrupt number 86 [write] 1: pend [read] 0: not pending 1: pending interrupt number 85 [write] 1: pend [read] 0: not pending 1: pending interrupt number 84 [write] 1: pend [read] 0: not pending 1: pending interrupt number 83 [write] 1: pend [read] 0: not pending 1: pending interrupt number 82 [write] 1: pend [read] 0: not pending 1: pending interrupt number 81 [write] 1: pend [read] 0: not pending 1: pending interrupt number 80 [write] 1: pend [read] 0: not pending 1: pending 31 30 29 28 27 26 25 24 bit symbol setpend read/write r r/w after reset 0 undefined function ?0? is read. interrupt number 94 [write] 1: pend [read] 0: not pending 1: pending interrupt number 93 [write] 1: pend [read] 0: not pending 1: pending interrupt number 92 [write] 1: pend [read] 0: not pending 1: pending interrupt number 91 [write] 1: pend [read] 0: not pending 1: pending interrupt number 90 [write] 1: pend [read] 0: not pending 1: pending interrupt number 89 [write] 1: pend [read] 0: not pending 1: pending interrupt number 88 [write] 1: pend [read] 0: not pending 1: pending 7 exceptions tmpm380/m382 tmpm380/m382 - 38 / 59 - tmpm380/m382 tmpm380/m382 - 39 / 59 - 7.6.2.14 interrupt clear-pending register 1 7 6 5 4 3 2 1 0 bit symbol clrpend read/write r/w after reset undefined function interrupt number 7 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 6 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 5 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 4 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 3 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 2 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 1 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 0 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 15 14 13 12 11 10 9 8 bit symbol clrpend read/write r/w after reset undefined function interrupt number 15 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 14 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 13 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 12 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 11 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 10 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 9 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 8 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 23 22 21 20 19 18 17 16 bit symbol clrpend read/write r/w after reset undefined function interrupt number 23 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 22 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 21 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 20 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 19 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 18 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 17 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 16 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 31 30 29 28 27 26 25 24 bit symbol clrpend read/write r/w after reset undefined function interrupt number 31 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 30 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 29 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 28 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 27 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 26 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 25 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 24 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 7 exceptions tmpm380/m382 tmpm380/m382 - 40 / 59 - tmpm380/m382 tmpm380/m382 - 41 / 59 - 7.6.2.15 interrupt clear-pending register 2 7 6 5 4 3 2 1 0 bit symbol clrpend read/write r/w after reset undefined function interrupt number39 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 38 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 37 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 36 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 35 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 34 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 33 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 32 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 15 14 13 12 11 10 9 8 bit symbol clrpend read/write r/w after reset undefined function interrupt number 47 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 46 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 45 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 44 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 43 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 42 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 41 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 40 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 23 22 21 20 19 18 17 16 bit symbol clrpend read/write r/w after reset undefined function interrupt number 55 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 54 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 53 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 52 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 51 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 50 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 49 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 48 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 31 30 29 28 27 26 25 24 bit symbol clrpend read/write r/w after reset undefined function interrupt number 63 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 62 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 61 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 60 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 59 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number58 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 57 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 56 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 7 exceptions tmpm380/m382 tmpm380/m382 - 42 / 59 - tmpm380/m382 tmpm380/m382 - 43 / 59 - 7.6.2.16 interrupt clear-pending register 3 7 6 5 4 3 2 1 0 bit symbol clrpend read/write r/w after reset undefined function interrupt number 71 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 70 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 69 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 68 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 67 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 66 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 65 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 64 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 15 14 13 12 11 10 9 8 bit symbol clrpend read/write r/w after reset undefined function interrupt number 79 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 78 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 77 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 76 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 75 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 74 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 73 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 72 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 23 22 21 20 19 18 17 16 bit symbol clrpend read/write r/w after reset undefined function interrupt number 87 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 86 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 85 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 84 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 83 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 82 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 81 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 80 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 31 30 29 28 27 26 25 24 bit symbol clrpend read/write r r/w after reset 0 undefined function ?0? is read. interrupt number 94 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 93 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 92 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 91 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 90 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 89 [write] 1: clear pending interrupt [read] 0: not pending 1: pending interrupt number 88 [write] 1: clear pending interrupt [read] 0: not pending 1: pending 7 exceptions tmpm380/m382 tmpm380/m382 - 44 / 59 - tmpm380/m382 tmpm380/m382 - 45 / 59 - 7.6.2.17 interrupt priority registers each inte rrupt is provide d with eight bi ts of an interrupt priority register. the following shows the addresses of the interr upt priority registers corresponding to interrupt numbers. 31 24 23 16 15 8 7 0 0xe000_e400 pri_3 pri_2 pri_1 pri_0 0xe000_e404 pri_7 pri_6 pri_5 pri_4 0xe000_e408 pri_11 pri_10 pri_9 pri_8 0xe000_e40c pri_15 pri_14 pri_13 pri_12 0xe000_e410 pri_19 pri_18 pri_17 pri_16 0xe000_e414 pri_23 pri_22 pri_21 pri_20 0xe000_e418 pri_27 pri_26 pri_25 pri_24 0xe000_e41c pri_31 pri_30 pri_29 pri_28 0xe000_e420 pri_35 pri_34 pri_33 pri_32 0xe000_e424 pri_39 pri_38 pri_37 pri_36 0xe000_e428 pri_43 pri_42 pri_41 pri_40 0xe000_e42c pri_47 pri_46 pri_45 pri_44 0xe000_e430 pri_51 pri_50 pri_49 pri_48 0xe000_e434 pri_55 pri_54 pri_53 pri_52 0xe000_e438 pri_59 pri_58 pri_57 pri_56 0xe000_e43c pri_63 pri_62 pri_61 pri_60 0xe000_e440 pri_67 pri_66 pri_65 pri_64 0xe000_e444 pri_71 pri_70 pri_69 pri_68 0xe000_e448 pri_75 pri_74 pri_73 pri_72 0xe000_e44c pri_79 pri_78 pri_77 pri_76 0xe000_e450 pri_83 pri_82 pri_81 pri_80 0xe000_e454 pri_87 pri_86 pri_85 pri_84 0xe000_e458 pri_81 pri_80 pri_89 pri_88 0xe000_e45c - pri_94 pri_93 pri_92 the number of bits to be used for assigning a priority varies with each product. this product uses three bits for assigning a priority. the following shows the fields of the interrupt priority registers for interrupt numbers 0 to 3. the interrupt priority registers for all other interrupt numbers have the identical fields. unused bits return ?0? when read, and writing to unused bits has no effect. 7 exceptions tmpm380/m382 tmpm380/m382 - 46 / 59 - 7 6 5 4 3 2 1 0 bit symbol pri_0 read/write r/w r after reset 0 0 function priority of interrupt number 0 ?0? is read. 15 14 13 12 11 10 9 8 bit symbol pri_1 read/write r/w r after reset 0 0 function priority of interrupt number 1 ?0? is read. 23 22 21 20 19 18 17 16 bit symbol pri_2 read/write r/w r after reset 0 0 function priority of interrupt number 2 ?0? is read. 31 30 29 28 27 26 25 24 bit symbol pri_3 read/write r/w r after reset 0 0 function priority of interrupt number 3 ?0? is read. tmpm380/m382 tmpm380/m382 - 47 / 59 - 7.6.2.18 vector table offset register 7 6 5 4 3 2 1 0 bit symbol tbloff read/write r/w r after reset 0 0 function offset value ?0? is read. 15 14 13 12 11 10 9 8 bit symbol tbloff read/write r/w after reset 0 function offset value 23 22 21 20 19 18 17 16 bit symbol tbloff read/write r/w after reset 0 function offset value 31 30 29 28 27 26 25 24 bit symbol tblba se tbloff read/write r r/w r/w after reset 0 0 0 function ?0? is read. table base offset value 7 exceptions tmpm380/m382 tmpm380/m382 - 48 / 59 - 7.6.2.19 system handler priority registers sys te m handler priority registers ha ve eight bits per each exception. the following shows the addresses of the system handler priority registers corresponding to each exception. 31 24 23 16 15 8 7 0 0xe000_ed18 pri_7 pri_6 (usage fault) pri_5 (bus fault) pri_4 (memory management) 0xe000_ed1c pri_11 (svcall) pri_10 pri_9 pri_8 0xe000_ed20 pri_15 (systick) pri_14 (pendsv) pri_13 pri_12 (debug monitor) the number of bits to be used for assigning a priority varies with each product. this product uses three bits for assigning a priority. the following shows the fields of the system handl er priority registers for memory management, bus fault and usage fault. the system handler priority regi sters for all other except ions have the identical fields. unused bits return ?0? when read, and writing to unused bits has no effect. 7 6 5 4 3 2 1 0 bit symbol pri_4 read/write r/w r after reset 0 0 function priority of memory management ?0? is read. 15 14 13 12 11 10 9 8 bit symbol pri_5 read/write r/w r after reset 0 0 function priority of bus fault ?0? is read. 23 22 21 20 19 18 17 16 bit symbol pri_6 read/write r/w r after reset 0 0 function priority of usage fault ?0? is read. 31 30 29 28 27 26 25 24 bit symbol pri_7 read/write r/w r after reset 0 0 function reserved ?0? is read. tmpm380/m382 tmpm380/m382 - 49 / 59 - 7.6.2.20 system handler control and state register 7 6 5 4 3 2 1 0 bit symbol svcall act usgfau lt act busfau lt act memfau lt act read/write r/w r r/w r r/w r/w after reset 0 0 0 0 0 0 function svcall 0: inactive 1: active ?0? is read. usage fault 0: inactive 1: active ?0? is read. bus fault 0: inactive 1: active memory management 0: inactive 1: active 15 14 13 12 11 10 9 8 bit symbol svcall pended busfau lt pended memfau lt pended usgfau lt pended systick act pendsv act monito r act read/write r/w r/w r/w r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function svcall 0: not pended 1: pended bus fault 0: not pended 1: pended memory management 0: not pended 1: pended usage fault 0: not pended 1: pended systick 0: inactive 1: active pendsv 0: inactive 1: active ?0? is read. debug monitor 0: inactive 1: active 23 22 21 20 19 18 17 16 bit symbol usgfau lt ena busfau lt ena memfau lt ena read/write r r/w r/w r/w after reset 0 0 0 0 function ?0? is read. usage fault 0: disable 1: enable bus fault 0: disable 1: enable memory management 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function ?0? is read. 7 exceptions tmpm380/m382 tmpm380/m382 - 50 / 59 - |